ZofzPCB

Is it possible to cover the solder mask layer topographically accurate on top of the copper layer ?
The current mask stack up has an air gap between solder mask an core, which is not real.

This would enable to simulate (using ANSYS HFSS) the impact of the solder mask layer, which is significant at higher frequencies > 5 GHz.

Yes, the concept of the layers is simple. Each layer has a defined Z-position and thickness.



And if it ever comes to the silkscreen layer, it will be even more gap.

So, for the SolderMask, I would need to create two sub-layers:

1. SolderMask AND NOT copper
2. SolderMask AND enlarged-copper

Also, the mid-layer air gap should be replaced by an extra core = BoardOutline AND NOT copper.

Now, the question is if this should be part of flattening, visible also in ZofzPCB native view, or only for the STEP export.
It also raises another question of a via tenting. That would be SolderMask AND NOT shrinked-drill.

Let me sort these things out in my mind.