What is the via barrel plating thickness when exporting a STEP?

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johnsg
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What is the via barrel plating thickness when exporting a STEP?

Post by johnsg »

I have the free version, so I cannot test this out.

My questions are:
1. What this the thickness of the via barrel plating, i.e. the thickness of copper used for the plating of a via wall, when I export a STEP file?
2. Can I set the thickness of the via barrel plating?

I'm asking because I am considering using ZofZ to generate step files for use in FEM software, both for thermal and electrical analysis. My companies designs are high current and vias play a significant role in carrying current and heat away from the active power devices (we have experimental data). The thickness of the via plating can have a large effect on this, and usually the via barrel wall plating is significantly thinner than the layer plating.

ZofZ looks attractive because it appears to be able to correctly export the barrels, whereas our current software only imports vias as solid, and converting them to the proper barrel shape is tedious and time-consuming. But, if the barrel wall thickness is wrong, it doesn't help us much.

Thanks,
John
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Zofz
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Re: What is the via barrel plating thickness when exporting a STEP?

Post by Zofz »

The barrel radius enlargement is 7.8um (constant BRenlarge = 1/128mm - a beautiful number with many zeros in the binary float representation). I didn't bring this value up to the UI for the sake of keeping the UI simple. It would belong to View/Render Effect Parameters Dialog, as those values are honored during rendering (and even during the file load in this case).
But to do it right, there is a related topic to solve:
  1. THT or metalized mounting holes: the manufacturer will drill the PCB with slightly bigger drills, so the end hole diameter after metalization is as specified in the drill file.
  2. Vias need to be narrow, even more narrow. In practice, nothing (like a pin) goes through the via holes, so to satisfy the annular ring (or the clearance to another net in a not connected layer), the manufacturer uses (mostly) the same drill diameter, letting the metalization grow into the hole, even closing it partially or fully.
There is some provision for distinguishing between holes and vias, for ODB++ (and Gerber in the IPC-356). I think providing a threshold diameter to distinguish the vias would be adequate for a start.
johnsg
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Re: What is the via barrel plating thickness when exporting a STEP?

Post by johnsg »

Thanks for the information.

For what it is worth, all our PCB vendors say that they aim for the finished hole size to be the diameter specified in the hole file. They calculate the necessary drill such that the finished hole meets the spec within their tolerance. They do not distinguish between vias and holes, at least for conventional drilled holes. The only distinguishing feature aside from diameter is between plated or non-plated.

I could see a potential issue with minimum wall-to-wall spacing for vias, but we get this number from our vendors, and never have complaints even when we space vias right at the minimum. So, I assuming that their rule already has a factor for this built in. We give them a typical fab notes file before we ask, which specifies a minimum hole or via wall thickness of 0.787 mil. Note that our fab notes also specify that the holes diameters in our drill file are to be the finished hole diameter, so that there is less opportunity for error.

We are only starting to use ODB++. I do not know if they specify them differently.

But, 7.8 um is way too thin. We have done a lot of work on this (simulation and experiment), so we are quite sure that our vendors meet or or exceed the 0.787 mil (20 um) minimum wall plating thickness.

Hope this is useful information.

John
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Zofz
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Re: What is the via barrel plating thickness when exporting a STEP?

Post by Zofz »

I am adding this functionality.
RenderEffects.png
RenderEffects.png (16.52 KiB) Viewed 1885 times
But what I found is that there is another variable defining the actual enlargement:
const double PlattingThickness = 0.02;
Setting it at 20um!
The former variable found was a contact tolerance for electrical connection testing.
If a PCB manufacturer provides hole diameter as specified, regardless of the diameter, the threshold should be zero - and I am setting this as the default value.
The PCB I am just now sending to the factory has two via diameters 0.1 and 0.2 (0.1 is layer 1-2, 0.2 is 1-6), where I needed to ask for a small clearance due to 0.5mm BGA fanout. And I could do it by allowing the metalization to grow inwards, possibly closing the via. (0.1 needs to be filled and capped anyway - via in the pad)
For my arrangement, the threshold would be, say, 0.3 as the next THT hole is about 0.7mm
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Zofz
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Re: What is the via barrel plating thickness when exporting a STEP?

Post by Zofz »

Feedback on my current PCB design:
"For the drills of final diameter 0.2mm x 1849 drilled with 0.3mm having copper pad of 0.45mm with annular ring of 0.075mm."
"As per our production requirement we need minimum 0.125mm annular ring (Measured form drill hole size)."

I have asked to relax the requirement of the final drill size to be 0.2, up to the via being even closed. This has added 0.05 to the existing 0.075 (=0.125) clearance, removing the problem. That would mean the via wall is 50um.

The same problem on the 0.1mm via was automatically corrected the same way, without talking to me. So, there is some kind of relaxation possibility detection based on the "blind" or "smallest" feature.

What does it mean for the visualization?

Am I right to introduce the THT/VIA threshold, displaying the hole metalization outwards and inwards to the original hole drill diameter?
(And is the typical metalization thickness 20 or 50um?)
johnsg
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Re: What is the via barrel plating thickness when exporting a STEP?

Post by johnsg »

Sorry for the delayed response.

I think that your proposed solution is useful. I think the issue is related to through vias vs microvias (usually laser drilled). Microvias are usually only between two adjacent layers, i.e. through one layer of insulation (sometimes two). They are often filled with copper plating, though they can be left open or filled and plated.

It would be nice to be able to specific the via type according to IPC standards. I do this for PCB fabrication, but right now this is done using a Fab Notes text file, and the via type is specified for all vias of a particular diameter. This is a holdover from using Gerbers, but perhaps ODB++ or IPC-2581 allows this to be specified.

For now, I think your current solution is a good start.

Thanks,
John
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Zofz
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Re: What is the via barrel plating thickness when exporting a STEP?

Post by Zofz »

I am now working on functionality related to the BOM. Publishing a version now would have a counterproductive effect, so I have time to decide. I learned that the specification always applies to the final hole, except for the micro vias, so we are in line on this topic. Closing vias through metallization is also dangerous due to acid traps. Implementing a threshold can also introduce a bit of mess, so I'll just add the drill wall thickness, as you suggest, maybe with presets. I have automatic micro via detection, and I should bring the conditions into this dialog box sooner or later. After the BOM and the part ordering function, the next topic is that I will try to qualify a PCB for production, hopefully I will learn about PCB classes and costs and implement more controls to qualify a given PCB.
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